The invention relates to radio receivers and transmitters, and more particularly to digital synthesizers for use in such equipment.
It is common in radio receiver and transmitter circuits to use direct digital synthesizers to generate a sinusoidal waveform for use in frequency conversion, modulation, and the like. Most commonly, waveform synthesis is accomplished by feeding the output of an accumulator to a discrete read-only-memory (ROM) containing a lookup table. For each value output by the accumulator, each of which represents a phase angle in the sinusoidal waveform cycle, the ROM provides an amplitude value for the waveform corresponding to the phase angle. The resulting successive digital amplitude values are fed to a digital-to-analog converter, which produces a digital (i.e., stepped) approximation of a sinusoidal waveform. With proper filtering, the higher frequency components contained in the waveform steps can be removed to produce a pure sinusoidal waveform.
This design, however, has several drawbacks. First, it requires a large amount of memory, which translates into large chip sizes, which frustrate miniaturization efforts. Second, accessing memory is relatively slow, which limits the ROM access rate. Finally, large chips dissipate large amounts of power.
An approach to solving the problems of the one ROM synthesis method is to view the phase angle of the sinusoidal waveform which is being synthesized as the sum of two angles. In accordance with trigonometric identities hereinafter discussed, the sinusoidal waveform can be synthesized as a function of values stored in two ROMs. While this approach helps to alleviate the problem, the memory requirements are still extensive.
It is therefore an object of the present invention to provide a direct digital synthesizer which requires less memory.
It is another object of the present invention to provide a direct digital synthesizer which conserves circuit board area.
It is a further object of the present invention to provide a direct digital synthesizer which increases synthesis speed.
It is an additional object of the present invention to provide a direct digital synthesizer which reduces power dissipation.
With these and other objects of the invention in view, the present invention digitally generates a sinusoidal waveform by dividing the sine wave into a plurality of coarse phase angle intervals, which are in turn divided into a plurality of intermediate phase angle intervals. The amplitude value for each coarse phase angle interval and intermediate phase interval is digitally constructed from a value representing the phase angle, and three different types of values stored in three separate memory devices. A coarse value, which provides the basic value for each coarse phase interval, is modified through combination with a slope value and a carry value for each intermediate phase angle interval. The phase angle is multiplied by the slope value at each intermediate phase angle interval, and the carry value is added to the result. This result is, in turn, added to the coarse value at each intermediate phase angle interval. The operation is repeated for each coarse interval to produce 180 degrees of a complete sine wave cycle. The entire operation is then repeated, and the values are negatived to produce the second 180 degrees of the sine wave cycle.
In a more detailed aspect of the invention, the values in the carry register are selected to provide the value 1 in a first portion of the intermediate phase interval and the value 0 in the second portion of the intermediate phase interval. Depending upon the coarse interval the first portion can precede or follow the second portion.
In a still further detailed aspect of the invention, the values in the carry register are chosen such that the portions of the intermediate interval having the value 1 constitutes three-fourths of the intermediate phase interval.
In yet another detailed aspect of the invention, the carry value is held in a carry register holds two digital bits, the first of which determines whether the value 1 is to be added at each intermediate phase interval, and the second of which determines whether that value will be added to the initial or the last three-fourths of the intermediate phase angle